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Timer calculator

STM32 Timer Calculator

PSC/ARR values, actual timer frequency, error, and APB timer clock doubling.

STM32 PSC and ARR calculator

Calculate timer register values from APB clock, APB prescaler, target frequency, and register limits.

STM32 timer clock is often doubled when the APB prescaler is greater than 1.
Timer clock
168.00 MHz
PSC
2
ARR
55999
Actual frequency
1000.000 Hz
Error
0 ppm

Register math uses (PSC + 1) * (ARR + 1), not PSC * ARR.

Formula notes

STM32 timer update frequency is timer_clock / ((PSC + 1) * (ARR + 1)). Many STM32 families double the timer clock when the APB prescaler is not 1, so check the reference manual clock tree.

What this calculator is for

Use this STM32 timer calculator to find prescaler and auto-reload register values for periodic interrupts, PWM output, capture timing, and simple time bases. Enter the APB clock and prescaler exactly as configured in RCC, then set the target frequency and register limits for the selected timer instance.

The result includes the timer clock, PSC, ARR, actual frequency, and frequency error. Keep those values together in firmware notes because a correct-looking register pair can still be wrong if the clock tree assumption is wrong.

Key parameters

  • APB clock: the bus clock after PLL and APB prescaler configuration.
  • APB prescaler: used to detect whether the timer peripheral clock is doubled.
  • Target frequency: the desired update event, PWM base frequency, or interrupt rate.
  • Max PSC and ARR: the register width limits for the exact timer, often 16-bit but sometimes wider.

APB timer-clock doubling

STM32 timers are a common source of off-by-two bugs. On many families, if the APB prescaler is 1, the timer clock equals the APB clock. If the APB prescaler is greater than 1, the timer clock is twice the APB clock. This lets timers keep higher timing resolution even when the peripheral bus is divided down.

Register limits

Most general-purpose timers use 16-bit PSC and ARR, while selected timers support 32-bit ARR. Set the limits to match the exact timer instance before copying values into firmware.

Choosing PSC and ARR for PWM

For PWM, the pair with the lowest frequency error is not always the most useful pair. A larger ARR gives finer duty cycle steps because the compare register has more counts to work with. If two combinations produce the same target frequency, prefer the one that leaves enough ARR resolution for the duty-cycle granularity you need.

Common configuration mistakes

  • Using APB clock directly when the timer clock is actually doubled.
  • Forgetting that PSC = 0 divides by one, not zero.
  • Copying 32-bit ARR assumptions to a 16-bit timer.
  • Changing PSC or ARR while running without understanding update-event buffering.
  • Enabling the timer but missing the GPIO alternate-function or NVIC interrupt configuration.

How to verify the values on hardware

For an interrupt timer, toggle a spare GPIO in the update interrupt and measure the period with a scope or logic analyzer. For PWM, measure both frequency and duty cycle at the output pin after alternate-function setup. If the measured value is exactly half or double the target, recheck the APB prescaler and timer-clock doubling rule before changing PSC and ARR.

Before copying to firmware

  • Confirm the APB clock after PLL and bus prescaler configuration.
  • Check whether the timer clock doubles when the APB prescaler is greater than 1.
  • Use the reported actual frequency and error when an exact integer match is not possible.

Frequently asked questions

How do I calculate STM32 timer prescaler and period values?

First determine the actual timer clock, including the APB timer-clock doubling rule. Then solve timer_clock / ((PSC + 1) * (ARR + 1)) for a PSC and ARR pair that fits the register limits and gives the closest actual frequency.

Why does STM32 timer math use PSC plus 1 and ARR plus 1?

Both registers are zero-based. A PSC value of 0 divides by 1, and an ARR value of 0 gives a one-count period. Direct PSC * ARR math is off by one and can produce a large timing error.

Why is my STM32 timer frequency twice what I expected?

On many STM32 families, when an APB prescaler is greater than 1, timers on that APB bus receive twice the APB clock. For example, an APB clock of 84 MHz with prescaler 2 can feed timers at 168 MHz.

Can I change an STM32 timer prescaler on the fly?

Yes, but the new PSC value is typically buffered and takes effect on an update event. For immediate application you can generate an update event, but that can reset the counter and affect update interrupts, so check the exact timer mode.

What should I check when an STM32 timer is not working?

Confirm the RCC clock is enabled, the APB clock is what you expect, the timer clock doubling rule is handled, PSC and ARR fit the selected timer width, update interrupts are enabled when needed, and the output pin is configured for the correct alternate function.